Compressor based approximate multiplier architectures for media processing applications

Approximate computing is an attractive technique to gain substantial improvement in the area, speed, and power applications where exact computation not required. This paper proposes two improved multiplier designs based on a new 4:2 approximate compressor circuit simplify hardware at partial product reduction stage. The proposed are targeted towards error-tolerant applications. Exhaustive error analysis has been carried out existing designs. results prove that architecture performs better than architectures without significant compromise quality metrics. Experimental show die-area consumed reduced upto 28%, 25.29% respectively comparison with accuracy.